mikeash.com pyblog/friday-qa-2012-12-28-what-happens-when-you-load-a-byte-of-memory.html comments

mikeash - 2014-11-26 02:40:14

Wed, 26 Nov 2014 02:40:14 GMT

There wouldn't be much if any difference between ARM32 and ARM64, since they're just two different modes of the same CPU, and those two modes almost certainly share the same memory controller hardware.

Mac Restore - 2014-11-13 01:07:34

Thu, 13 Nov 2014 01:07:34 GMT

How about the different between ARM 32-bit architecture and 64-bit for loading a byte of memory?

Manish - 2013-02-09 17:09:44

Sat, 09 Feb 2013 17:09:44 GMT

Great article!
The succinct manner in which the article has been written over-rides the complex stuff which is conveyed. Very informative stuff,

Thanks

foFox - 2013-01-13 03:20:16

Sun, 13 Jan 2013 03:20:16 GMT

As usual great stuff :)

David Smith - 2013-01-03 01:45:23

Thu, 03 Jan 2013 01:45:23 GMT

A fun (and ballpark-accurate) rule of thumb that I recalled while reading the cache section is each time you double the size of a given cache, its miss rate drops by roughly a factor of sqrt(2). There's a much more detailed analysis at http://researcher.watson.ibm.com/researcher/files/us-viji/cache-miss-sqrt2.pdf

Rainer Brockerhoff - 2012-12-29 13:16:59

Sat, 29 Dec 2012 13:16:59 GMT

There's multiple levels in absolutely everything, just look at this: http://abstrusegoose.com/strips/rube_goldberg_large.PNG and it's grossly simplified at every level!

mikeash - 2012-12-28 23:41:50

Fri, 28 Dec 2012 23:41:50 GMT

Bram Stolk: Note that the constraints in hardware are totally different from what we're used to in software. If you're willing to pay for the transistors, you can execute something like this completely in parallel:



for(int i = 0; i < TLB_SIZE; i++)

    if(tlb[i].addr = searchAddr)

        return tlb[i].mapping;

You basically have a different circuit for every iteration of the loop, and they all run simultaneously. Stuff like this is why modern processors are able to do so much more work per clock cycle than older processors, and not just run at a higher clock rate. The continuing shrinkage of integrated circuit transistors means that more and more transistors are available for fancy parallel execution of our code.

Just for an amusing comparison, an Intel 386, which is mostly functionally equivalent to a modern Intel processor, minus the 64-bit stuff and some other fancy bits, had about 275,000 transistors. An i7 has about two billion transistors. That will buy you a lot of parallel TLB search iterations.

SSteve - 2012-12-28 21:33:53

Fri, 28 Dec 2012 21:33:53 GMT

When I start to think about all the levels of things going on in the computer I'm amazed that anything actually happens. And it always brings this to mind:

http://xkcd.com/676/

Rainer Brockerhoff - 2012-12-28 20:20:50

Fri, 28 Dec 2012 20:20:50 GMT

The TLB is usually an associative device, meaning it can compare a page address against all of its entries in a single clock cycle, or even a fraction of that. Expensive to implement in silicon, but worth it. I think modern CPUs have multiple-level TLBs, even.

warmi - 2012-12-28 19:55:29

Fri, 28 Dec 2012 19:55:29 GMT

Multiple caching levels have all sorts of implications including things like the fact that using simple sequential containers ( arrays) for linear searches of small data, tends to faster than elaborate structures like hashes/maps ...

In general, data-oriented programming is making comeback in performance oriented code ( games etc)

http://justinliew.com/blog/?p=2890

Bram Stolk - 2012-12-28 16:33:41

Fri, 28 Dec 2012 16:33:41 GMT

How is the TLB search performed?
Hopefully not a linear search?
More memory use would mean more entries, would mean a slower look up?
That sounds horrible.